This invention relates to field-effect transistor fabrication.
The present invention achieves the goal of a field-effect transistor in which a single metalization step realizes the gate contact and the source/drain contacts--a single metalization arrangement which is practical, economically viable and does not require separate masking steps for the Schottky barrier and ohmic junction characteristics of the gate contact and the source/drain contacts respectively. The invention arises from compromise between several semiconductor device disciplines--including material growth, device metalization, and material deposition. The achieved field-effect transistor is technically and economically viable for use in analog transistor applications extending to the microwave and millimeter wave spectral regions for example.
Several concepts appearing in the present invention also appear in the patent and publication literature as stand-alone concepts, concepts used in a different setting or concepts combined in less than the combination contemplated in the present invention. The present invention is, however, believed to represent a novel and unobvious combination of such concepts to achieve a useful result. The concept of using the same metal in parts of the source, drain and gate structure of a field-effect transistor for example appears in a certain form in transistors fabricated some years ago when the self aligned gate structure was new in the art. Examples of this same metal concept appear for example in the two related RCA patents of Napoli et al., U.S. Pat. No. 3,764,865 and U.S. Pat. No. 3,861,024. The same metal concept also appears in the two related Westinghouse patents of Kim, U.S. Pat No. 3,855,690 and U.S. Pat. No. 3,943,622.
In each of these four patents however, the disclosed transistor involves use of a common metal to connect to an already formed source/drain ohmic contact and to form the Schottky barrier gate contact. In the silicon material used in the devices of these four patents an ohmic contact is moreover achieved with the mere addition of another layer of material and does not require the alloying, annealing and other complexities often needed for a group III-V semiconductor device ohmic contact. The present invention is believed distinguished over the disclosure of these older patents by its use the same metal to actually form the gate contact as to form the source/drain contacts of the transistor. Moreover in the present invention these source/drain contacts are achieved in a non-alloyed fashion.
The U.S. Pat. No. 4,961,194 of S. Kuroda et al., describes gallium arsenide MESFET and HEMT devices which use the combination of non-alloyed ohmic contacts, same metal electrodes, acetone solvent removal of photoresist coatings, ion implanted device separation areas, selective etching and etch stopping at the surface of a device layer. Although each of these concepts may be used in the present invention additional concepts not disclosed in the Kuroda et al. patent are also a part of the present invention and provide significant distinction over the Kuroda et al. patent. The Kuroda et al. patent for example does not disclose the use of a permanent secondary mask and passivation material layer nor the concept of a gate aperture recess received in a gate window nor the precise and time effective termination of etching operations as is accomplished in applicants' invention. In view of the similar areas of work and in the interest of minimizing the size of the present patent document, the contents of the of S. Kuroda et al. U.S. Pat. No. 4,961,194 are, however, hereby incorporated by reference herein.
An article published in the technical literature some years ago is also of interest with respect to the single metal transistor concept and is additionally of interest with respect to the use of non-alloyed ohmic contacts in a field-effect transistor. This article "A New Fabrication Technology for AlGaAs/GaAs HEMT LSI's Using InGaAs Non-alloyed Ohmic Contacts" is authored by S. Kuroda et al. as apparently the same S. Kuroda et al., as appears in the above identified U.S. Pat. No. 4,961,194, and appears at page 2196 in the Institute of Electrical and Electronic Engineers Transactions on Electron Devices, Volume 36, number 10, October, 1989. This Kuroda article is in fact of an especially enlightening contrast in nature with respect to the present invention since it teaches the use of a complex etching sequence during formation of the transistor elements and the present invention avoids use of this sequence in favor of a more practical and less costly procedure.
In a somewhat related situation the technical article "All-Refractory GaAs FET Using Amorphous TiWSi.sub.x Source/Drain Metalization and Graded In.sub.x Ga.sub.1-x As Layers" authored by N. Papanicolaou which appears at page 7 in the Institute of Electrical and Electronic Engineers Electron Devices Letters, volume 15, number 1, January, 1994 discloses the use of non-alloyed ohmic contacts in a gallium arsenide field-effect transistor. The Papanicolaou article, however, relates to the fabrication of a high temperature field-effect transistor device, a device having refractory metal elements and involving the use of Tungsten metal. The Papanicolaou article also presents an informative discussion of the non-alloyed ohmic contact art.
The inventors of the present invention have also found the textbook "Modern GaAs Processing Methods" authored by Ralph Williams, Artech House, of Boston and London, to be of assistance in explaining and understanding certain aspects attending the present invention including its relationship with the prior art. In the further interest of minimizing the size of the present patent document, the contents of this Ralph Williams, Artech House textbook are therefore hereby also incorporated by reference herein.
Non-alloyed ohmic contacts are additionally disclosed in several published technical journal articles as follows.
1. Ohmic Contacts to n-GaAs Using Graded Band Gap Layers of Ga.sub.1-x In.sub.x As Grown by Molecular Beam Epitaxy, authored by J. M. Woodall et al., and appearing at page 626 in the J. Vacuum. Science. Technology. Vol 19, number 3, September/October 1981. PA1 2. HEMT with Non-alloyed Ohmic Contacts Using n.sup.+ -InGaAs Cap Layer, authored by S. Kuroda et al., and appearing at page 389 in the IEEE Electron Device Letters, Volume EDL-8, number 9, September 1987. PA1 3. Extremely Low Non-alloyed and Alloyed Contact Resistance Using an InAs Cap Layer on InGaAs by Molecular-Beam Epitaxy, authored by C. K. Peng et al., and appearing at page 429 in the J. Applied. Physics. Volume 64, number 1, Jul. 1, 1988. PA1 4. Non-Alloyed Ohmic Contacts to n-GaAs Using Compositional Graded In.sub.x Ga.sub.1-x As Layers, authored by T. Nittono et al., and appearing at pages 1718-1722 in the Japanese Journal of Applied Physics, Volume 27, number 9, September 1988. PA1 5. Extremely Low Contact Resistances for AlGaAs/GaAs Modulation-Doped Field-Effect Transistor Structures, authored by A. Ketterson et al., and appearing at page 2305 in the J. Applied. Physics. Volume 57, number 6. PA1 providing a transistor-divided gallium arsenide semiconductor material field-effect transistor wafer wherein a channel layer is covered by an ohmic connection layer that is overlaid by a secondary mask layer; PA1 forming a gate window recess extending through said secondary mask layer and down to said ohmic connection layer using a temporary first photoresist mask etching sequence; PA1 covering said secondary mask layer and said exposed gate window recess portion of said ohmic connection layer with a second and then a third temporary photoresist mask layers; PA1 opening source and drain recess apertures through said second and third temporary photoresist mask layers of each said transistor using an exposure and etching sequence, said source and drain recess apertures extending down to secondary mask layer; PA1 dissolving said third temporary photoresist layer from coverage of said second photoresist layer; PA1 defining a gate aperture position and gate aperture size in said second photoresist layer in said gate window recess using an electron beam lithography exposure and development sequence; PA1 etching a gate contact recess aperture through said ohmic connection layer at said gate aperture position in said gate window location using a selective etch sequence, said gate contact recess aperture extending down to said channel layer; PA1 said ohmic connection material underlying said source and drain locations being protected during said selective etching sequence by said permanent secondary mask and passivation material layer; PA1 etching away said permanent secondary mask and passivation material layer down to said ohmic connection material layer in said source and drain locations; PA1 said second temporary photoresist mask layer covering said permanent secondary mask and passivation material layer surrounding said gate window location and said source and drain locations being inert to said etching away step; PA1 depositing contact metal over said channel layer in said gate contact recess aperture, over said ohmic connection material layer in said source and drain locations, and incidentally over said second temporary photoresist mask layer around said gate window location and said source and drain locations; PA1 said contact metal forming a nonlinear Schottky barrier electrical contact relationship with said channel layer semiconductor material in said gate contact recess aperture and a non-alloyed linear electrical resistance ohmic contact relationship with said ohmic connection semiconductor material layer in said source and drain locations; PA1 removing said second temporary photoresist layer from said wafer, said removing simultaneously performing a metal lift-off clearing of contact metal around said gate window and said source and drain locations of said transistor.
Although each of these documents from the prior art may relate to an aspect of the present invention it is believed as indicated above that the invention as described herein represents the first combination of the plurality of concepts and compromises necessary to achieve a successful single metal, non-alloyed contact, selective etching-achieved, and secondary mask-inclusive field-effect transistor.